In designing complex systems like today's integrated circuits, where multiple clocks are used, the skew between clocks is often a crucial issue. This is particularly important when the integrated circuit has already been fabricated and it then becomes important to change the delay or skew between clocks. High frequency clock signals can be routed throughout an integrated circuit to multiple blocks of devices such as a hardware accelerators, DSP processors, and random access memories. It is desirable to have clock signals arrive at all hardware blocks at precisely controlled times, which may not be simultaneous. If the correct skew between the competing clocks is not properly set during the design of the integrated circuit, there would be a possibility for race conditions in the circuit and thus system failure. Once the integrated circuit is fabricated skew between clocks is hard tuned i.e. the relationship between the various clocks and the system can not be changed without a mask change which may be very costly and time consuming.
To design clock circuitry and properly set clock skew within an integrated circuit most designers typically use simulation tools. The problem is that simulation tools do not necessarily match the post fabrication characteristics of the integrated circuit. Discrepancies between the simulation models and the physical chip leaves the system susceptible to variations in delays and circuit timing that may not be accounted for. One of the most prevalent variations of this type is clock skew. Designers try to accommodate for clock skew variations in their designs by placing known delays in the circuit or placing clock uncertainties in the design constraints. These techniques usually yields only marginal results.
Another method of solving variations in clock skew is to use more realistic simulation delay models. These models may be developed by extracting the post layout and fabrication parasitic values in order to modify the models. This technique still requires the integrated circuit to be re-simulated with the new models. The integrated circuit must then go back through the fabrication and testing process. Using this technique has the problem of requiring extensive time to re-simulate and complete a second fabrication of the integrated circuit, which may not be possible due to the ever increasing time to market pressure. Even in scenarios where post layout RC parasitic values are taken into account, there would be no guarantee that the fabricated integrated circuit will behave as it was predicted because the models, due to their simplicity, do not necessarily follow the physical design parameters.